Writing
Jason Yu
@verilogproTracked since May 2026
creating digital design and verification articles.
Observed Aug 29, 2026 · staleModeled revenue
Paid members
8
0% · 30-day rate from 23 observed days
Total audience
20
incl. free followers
Estimated monthly gross
$16
$8–$24 modeled range
Starting price
$1/mo
5 membership tiers
Pricing and benefits captured publicly
Membership tiersPatreon is not exposing patron counts by tier for this creator, so this section shows public prices and benefits only.
$0/moFreePublic prices and benefits only
$1/moLoonie Learner - Pledge $1 or more per articleJoin me on this journey of continuous learning by supporting at $1 per article. You're officially a Loonie Learner! By joining this community, you get access to my patron-only feed, where I'll share quick tips that aren't long enough to become articles, AND you can download article code example directly here. No need to re-enter your email and download from Verilogpro website anymore!
A loonie is a Canadian $1 coin.
$5/moAdvisory Board Member - Pledge $5 or more per articleLike a leap to democracy, supporting at $5 or more per article, YOU GET TO VOTE! You join the Verilogpro advisory board, have a say on the direction of the website by pitching ideas and voting on future blog articles that I research and write. Voting is fun. Voting is power!
$10/moExecutive Board Member - Pledge $10 or more per articleSupporting at $10 or more per article, you become an EXECUTIVE MEMBER on my Verilogpro advisory board!Name on my supporters page at Verilogpro.comAccess to early drafts of my articles, and some that were never published
Did you know we use plastic bills in Canada? Just thought you should know.
$25/moYou can be my boss! - Pledge $25 or more per articleSupporting at $25 or more per article, YOU CAN BE MY BOSS! Call me up to work at night! Make me write a new article! Boss me around to do your chores! You can do all of that, and I will STILL be grateful to you!
You'll get everything in the previous tiers, I'll also write you a handwritten thank you card to show my appreciation.
There is no $25 bill in Canada, I just thought it's a nice number.
Growth signals: Jason Yu
0%
Membership8 paid members · 30-day rate from 23 observed days
898
May 202618 weeks trackedNow
Jason Yu8 members · $16/mo
The chart only uses Jason Yu's observed public history. Comparison peers are listed below, but comparable trend series are not available yet.
Where Jason Yu ranks
Creator comparisonsCompare within
#1of 7 measured
Paid members in Recommended cohort
Semantic matches are not ready, so this fixed cohort uses the best available category, audience, pricing, and cadence evidence.
Ranking data · includes stale rows| Rank | Creator and why included | Paid members | Gap vs Jason Yu | Freshness |
|---|---|---|---|---|
| #1 |  Jason YuProfileWritingPaid members position in Recommended cohort | 8 | Reference | Aug 29, 2026Stale |
| #1 |  JobbeWritingCategory, audience, pricing & cadence | 8 | Same value | Aug 29, 2026 |
| #1 |  LucronWritingCategory, audience, pricing & cadence | 8 | Same value | Aug 29, 2026 |
| #1 |  LupineKingWritingCategory, audience, pricing & cadence | 8 | Same value | Aug 19, 2026 |
| #1 |  The_LaurentWritingCategory, audience, pricing & cadence | 8 | Same value | Aug 29, 2026 |
The rank uses the full fixed cohort. This table shows up to five creators around Jason Yu; the coverage summary above still counts everyone.
Recent posts
What they publish7Profile posts1 postLast month33.3%Members-only
Previews available for 14 of 7 posts
Article Latest postPublicVerilog Generate Configurable RTL DesignsMy new post "Verilog Generate Configurable RTL Designs" is live on Verilogpro!
Jan 31, 2018 0 likes 0 commentsParameterized task/function arguments using static classesI recently saw a coworker use a SV class in design RTL. At first I thought he had made a mistake and there was no way that could be synthesizable. But it turned out he was correct.ArticleMay 10, 2017Public 0 0My new post is live!May 2, 2017ArticleMay 2, 2017$1 tier & up 0 0My Top 4 Verilog and SystemVerilog papersMay 1, 2017ArticleMay 1, 2017$1 tier & up 0 0Three takeaways from my next postApr 27, 2017ArticleApr 27, 2017Public 0 0Static vs automatic declaration for tasks and functionsNoticed this forum post today about static vs automatic functions and tasks in SystemVerilog. I understood that tasks and functions that are not within a class are by default static lifetime. But I wonder if a function or task that has automatic lifetime is synthesizable?Articletoday at Aug 29 crawlPublic 0 0We're live! Free posts for a while!Woohoo, we're live! I'm excited to launch the Verilogpro patreon page, and I invite you to join me on this journey to discover new techniques, coding styles, to use Verilog and SystemVerilog for digital design and verification!ArticleApr 23, 2017Public 0 0Verilog Generate Configurable RTL DesignsMy new post "Verilog Generate Configurable RTL Designs" is live on Verilogpro!ArticleJan 31, 2018Public 0 0Parameterized task/function arguments using static classesI recently saw a coworker use a SV class in design RTL. At first I thought he had made a mistake and there was no way that could be synthesizable. But it turned out he was correct.ArticleMay 10, 2017Public 0 0View 0 commentsMy new post is live! May 2, 2017ArticleMay 2, 2017$1 tier & up 0 0View 0 commentsMy Top 4 Verilog and SystemVerilog papers May 1, 2017ArticleMay 1, 2017$1 tier & up 0 0Three takeaways from my next postApr 27, 2017ArticleApr 27, 2017Public 0 0
Research actions
Work with this creator
Save, compare, or return to the Explore view you came from.